MC9S12P128 Datasheet, PDF (365/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Serial Communication Interface (S12SCIV5)
Register
Name
Bit 7
6
5
4
3
2
0x0004
R TDRE
TC
RDRF
IDLE
OR
NF
SCISR1 _W
0x0005
R
0
SCISR2
AMAP
W
0
TXPOL
RXPOL
BRK13
0x0006
R
R8
0
0
0
0
SCIDRH _W
T8
0x0007
R
R7
R6
R5
R4
R3
R2
SCIDRL _W
T7
T6
T5
T4
T3
T2
1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero.
2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one.
= Unimplemented or Reserved
Figure 11-2. SCI Register Summary (Sheet 2 of 2)
1 _{Those registers are accessible if the AMAP bit in the SCISR2 register is set to zero}
2 _{Those registers are accessible if the AMAP bit in the SCISR2 register is set to one}
1
FE
TXDIR
0
R1
T1
Bit 0
PF
RAF
0
R0
T0
11.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL)
Module Base + 0x0000
R
W
Reset
7
IREN
0
6
TNP1
5
TNP0
4
SBR12
3
SBR11
2
SBR10
0
0
0
0
0
Figure 11-3. SCI Baud Rate Register (SCIBDH)
1
SBR9
0
0
SBR8
0
Module Base + 0x0001
R
W
Reset
7
SBR7
0
6
SBR6
5
SBR5
4
SBR4
3
SBR3
2
SBR2
0
0
0
0
0
Figure 11-4. SCI Baud Rate Register (SCIBDL)
1
SBR1
0
0
SBR0
0
Read: Anytime, if AMAP = 0. If only SCIBDH is written to, a read will not return the correct data until
SCIBDL is written to as well, following a write to SCIBDH.
Write: Anytime, if AMAP = 0.
NOTE
Those two registers are only visible in the memory map if AMAP = 0 (reset
condition).
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
365