MC9S12P128 Datasheet, PDF (295/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Bus Clock Domain
CPU
Init Request
INITRQ
INITAK
Flag
sync.
INITAK
SYNC
CAN Clock Domain
sync.
INITRQ
INIT
Flag
SYNC
INITAK
Figure 8-45. Initialization Request/Acknowledge Cycle
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by
using a special handshake mechanism. This handshake causes additional synchronization delay (see
Section Figure 8-45., “Initialization Request/Acknowledge Cycle”).
If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus
clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the
INITAK flag is set. The application software must use INITAK as a handshake indication for the request
(INITRQ) to go into initialization mode.
NOTE
The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and
INITAK = 1) is active.
8.4.5 Low-Power Options
If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving.
If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power
consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption
is reduced by stopping all clocks except those to access the registers from the CPU side. In power down
mode, all clocks are stopped and no power is consumed.
Table 8-38 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes
is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits.
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
295