MC9S12P128 Datasheet, PDF (238/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.4.6.2 PLL Engaged External Mode (PEE)
In this mode, the Bus clock is based on the PLL clock as well (like PEI). The reference clock for the PLL
is based on the external oscillator. The adaptive spike filter is active and uses the VCOCLK to qualify the
status of the external oscillator clock.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock.
This mode can be entered from default mode PEI by performing the following steps:
1. Configure the PLL for desired bus frequency.
2. Program the reference divider (REFDIV[3:0] bits) to divide down Oscillator frequency if
necessary.
3. Enable the external Oscillator (OSCE bit).
Since the adaptive spike filter uses VCOCLK (from PLL) to continuously qualify the external oscillator
clock, losing PLL lock status (LOCK=0) means losing the oscillator status information as well
(UPOSC=0).
The impact of losing the oscillator status in PEE mode is as follows:
• The MSCAN module, which can be configured to run on the oscillator clock, may need to be re-
configured.
Application software needs to be prepared to deal with the impact of losing the oscillator status at any time.
7.4.6.3 PLL Bypassed External Mode (PBE)
In this mode, the Bus clock is based on the external oscillator clock. The reference clock for the PLL is
based on the external oscillator. The adaptive spike filter is active and uses the VCOCLK to qualify the
status of the external oscillator clock.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock.
This mode can be entered from default mode PEI by performing the following steps:
1. Make sure the PLL configuration is valid: Program the reference divider (REFDIV[3:0] bits) to
divide down Oscillator frequency if necessary.
2. Enable the external Oscillator (OSCE bit)
3. Wait for Oscillator to start up (UPOSC=1)
4. Select the Oscillator clock as Bus clock (PLLSEL=0)
Since the adaptive spike filter uses VCOCLK (from PLL) to continuously qualify the external oscillator
clock, losing PLL lock status (LOCK=0) means losing the oscillator status information as well
(UPOSC=0).
The impact of losing the oscillator status in PBE mode is as follows:
• The MSCAN module, which can be configured to run on the oscillator clock, may need to be re-
configured.
S12P-Family Reference Manual, Rev. 1.12
238
Freescale Semiconductor