MC9S12P128 Datasheet, PDF (480/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Timer Module (TIM16B8CV2) Block Description
Read: Anytime
Write: Anytime
Table 14-5. OC7D Field Descriptions
Field
Description
7:0
Output Compare 7 Data — A channel 7 output compare can cause bits in the output compare 7 data register
OC7D[7:0] to transfer to the timer port data register depending on the output compare 7 mask register.
14.3.2.5 Timer Count Register (TCNT)
Module Base + 0x0004
R
W
Reset
15
TCNT15
0
14
TCNT14
13
TCNT13
12
TCNT12
11
TCNT11
10
TCNT10
0
0
0
0
0
Figure 14-10. Timer Count Register High (TCNTH)
9
TCNT9
0
9
TCNT8
0
Module Base + 0x0005
7
R
TCNT7
W
6
TCNT6
5
TCNT5
4
TCNT4
3
TCNT3
2
TCNT2
1
TCNT1
0
TCNT0
Reset
0
0
0
0
0
0
0
0
Figure 14-11. Timer Count Register Low (TCNTL)
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
Read: Anytime
Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1).
The period of the first count after a write to the TCNT registers may be a different size because the write
is not synchronized with the prescaler clock.
S12P-Family Reference Manual, Rev. 1.12
480
Freescale Semiconductor