MC9S12P128 Datasheet, PDF (486/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Timer Module (TIM16B8CV2) Block Description
14.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Module Base + 0x000E
7
R
C7F
W
6
C6F
5
C5F
4
C4F
3
C3F
2
C2F
1
C1F
0
C0F
Reset
0
0
0
0
0
0
0
0
Figure 14-20. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
Table 14-15. TRLG1 Field Descriptions
Field
7:0
C[7:0]F
Description
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN is set to one.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel
(0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
14.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Module Base + 0x000F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
TOF
W
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 14-21. Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 is set to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
S12P-Family Reference Manual, Rev. 1.12
486
Freescale Semiconductor