MC9S12P128 Datasheet, PDF (529/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Electrical Characteristics
In Table A-27 the timing characteristics for master mode are listed.
Table A-27. SPI Master Mode Timing Characteristics
Num
1
1
2
3
4
5
6
9
10
11
12
13
C
Characteristic
D SCK frequency
D SCK period
D Enable lead time
D Enable lag time
D Clock (SCK) high or low time
D Data setup time (inputs)
D Data hold time (inputs)
D Data valid after SCK edge
D Data valid after SS fall (CPHA = 0)
D Data hold time (outputs)
D Rise and fall time inputs
D Rise and fall time outputs
Symbol
Min
Typ
f_sck
1/2048
—
t_sck
2
—
t_lead
—
1/2
t_lag
—
1/2
t_wsck
—
1/2
t_su
8
—
t_hi
8
—
t_vsck
—
—
t_vss
—
—
t_ho
20
—
t_rfi
—
—
t_rfo
—
—
Max
1/2
2048
—
—
—
—
—
29
15
—
8
8
Unit
f_bus
t_bus
t_sck
t_sck
t_sck
ns
ns
ns
ns
ns
ns
ns
A.11.2 Slave Mode
In Figure A-7 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
SS
(Input)
SCK
(CPOL = 0)
(Input)
SCK
(CPOL = 1)
(Input) ¹⁰
7
MISO
(Output)
2
See
Note
1
12
4
4
12
Slave MSB
9
Bit MSB-1 . . . 1
13 3
13
11
11
Slave LSB OUT
MOSI
(Input)
5
6
MSB IN
Bit MSB-1. . . 1
LSB IN
NOTE: Not defined
Figure A-7. SPI Slave Timing (CPHA = 0)
8
See
Note
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
529