MC9S12P128 Datasheet, PDF (107/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Chapter 3 S12P Memory Map Control (S12PMMCV1)
Table 3-1. Revision History Table
Table 3-2.
Rev. No.
Date
(Item No.) (Submitted By)
Sections
Affected
Substantial Change(s)
01.03
01.04
01.04
18.APR.2008
27.Jun.2008
11.Jul.2008
Section 3.3.2.3,
“Program Page
Index Register
(PPAGE)”
Corrected the address offset of the PPAGE register (on page 3-112)
Section 3.5.1,
“Implemented Removed “Table 1-9. MC9S12P Derivatives”
Memory Map”
Removed references to the MMCCTL1 register
3.1 Introduction
The S12PMMC module controls the access to all internal memories and peripherals for the CPU12 and
S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip
ressources. Figure 3-1 shows a block diagram of the S12PMMC module.
3.1.1 Glossary
Term
Local Addresses
Global Addresse
Aligned Bus Access
Misaligned Bus Access
NS
SS
Unimplemented Address Ranges
P-Flash
D-Plash
NVM
IFR
Table 3-3. Glossary Of Terms
Definition
Address within the CPU12’s Local Address Map (Figure 3-10)
Address within the Global Address Map (Figure 3-10)
Bus access to an even address.
Bus access to an odd address.
Normal Single-Chip Mode
Special Single-Chip Mode
Address ranges which are not mapped to any on-chip ressource.
Program Flash
Data Flash
Non-volatile Memory; P-Flash or D-Flash
NVM Information Row. Refer to FTMRC Block Guide
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
107