MC9S12P128 Datasheet, PDF (223/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
Table 7-17. Trimming Effect of APITR
Bit
APITR[1]
APITR[0]
Trimming Effect
Decreases period less than APITR[2]
Decreases period less than APITR[1]
7.3.2.17 Autonomous Periodical Interrupt Rate High and Low Register
(CPMUAPIRH / CPMUAPIRL)
The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical
interrupt rate.
0x02F4
R
W
Reset
7
APIR15
6
APIR14
5
APIR13
4
APIR12
3
APIR11
2
APIR10
1
APIR9
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-21. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)
0
APIR8
0
0x02F5
R
W
Reset
7
APIR7
6
APIR6
5
APIR5
4
APIR4
3
APIR3
2
APIR2
1
APIR1
0
0
0
0
0
0
0
Figure 7-22. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)
0
APIR0
0
Read: Anytime
Write: If APIFE=0, then write anytime, else writes have no effect.
Table 7-18. CPMUAPIRH / CPMUAPIRL Field Descriptions
Field
Description
15-0
Autonomous Periodical Interrupt Rate Bits — These bits define the timeout period of the API. See Table 7-
APIR[15:0] 19 for details of the effect of the autonomous periodical interrupt rate bits.
The period can be calculated as follows depending on logical value of the APICLK bit:
APICLK=0: Period = 2*(APIR[15:0] + 1) * f_ACLK
APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock period
Table 7-19. Selectable Autonomous Periodical Interrupt Periods
APICLK
0
APIR[15:0]
0000
Selected Period
0.2 ms⁽¹⁾
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
223