MC9S12P128 Datasheet, PDF (211/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
NOTE
After writing CPMUCLKS register, it is strongly recommended to read
back CPMUCLK register to make sure that write of PLLSEL, RTIOSCSEL
and COPOSCSEL was successful.
Table 7-5. CPMUCLKS Descriptions
Field
Description
7
PLLSEL
6
PSTP
3
PRE
PLL Select Bit
This bit selects the PLLCLK as source of the System Clocks (Core Clock and Bus Clock).
PLLSEL can only be set to 0, if UPOSC=1.
UPOSC= 0 sets the PLLSEL bit.
Entering full stop mode sets the PLLSEL bit.
0 System clocks are derived from OSCCLK if Oscillator is up (UPOSC=1, f_bus = f_osc / 2.
1 System clocks are derived from PLLCLK, f_bus = f_PLL / 2.
Pseudo Stop Bit
This bit controls the functionality of the oscillator during Stop Mode.
0 Oscillator is disabled in Stop Mode.
1 Oscillator continues to run in Stop Mode (Pseudo Stop), option to run RTI and COP.
Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.
Note: When starting up the external Oscillator (either by programming OSCEN bit to 1 or on exit from full stop
mode with OSCEN bit is already 1) the software must wait for a minimum time equivalent to the startup-
time of the external Oscillator t_UPOSC before entering Pseudo Stop Mode.
RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop Mode.
0 RTI stops running during Pseudo Stop Mode.
1 RTI continues running during Pseudo Stop Mode if RTIOSCSEL=1.
Note: If PRE=0 or RTIOSCSEL=0 then the RTI will go static while Stop Mode is active. The RTI counter will not
be reset.
2
PCE
COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop Mode.
0 COP stops running during Pseudo Stop Mode
1 COP continues running during Pseudo Stop Mode if COPOSCSEL=1
Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop Mode is active. The COP counter will
not be reset.
1
RTI Clock Select— RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the
RTIOSCSEL RTIOSCSEL bit re-starts the RTI timeout period.
RTIOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the RTIOSCSEL bit.
0 RTI clock source is IRCCLK.
1 RTI clock source is OSCCLK.
0
COP Clock Select— COPOSCSEL selects the clock source to the COP. Either IRCCLK or OSCCLK. Changing
COPOSCSE the COPOSCSEL bit re-starts the COP timeout period.
L
COPOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the COPOSCSEL bit.
0 COP clock source is IRCCLK.
1 COP clock source is OSCCLK
7.3.2.7 S12CPMU PLL Control Register (CPMUPLL)
This register controls the PLL functionality.
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
211