MC9S12P128 Datasheet, PDF (230/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
0x02FA
7
6
5
4
3
2
1
0
R
0
OSCE
OSCBW
W
OSCFILT[4:0]
Reset
0
0
0
0
0
0
0
0
Figure 7-29. S12CPMU Oscillator Register (CPMUOSC)
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE.
Write to this register clears the LOCK and UPOSC status bits.
NOTE.
If the chosen VCOCLK-to-OSCCLK ratio is not an integer number,
then the filter can not be used and the OSCFILT[4:0] bits must be set to
0.
Field
7
6
4-0
Table 7-21. CPMUOSC Field Descriptions
Description
Oscillator Enable Bit — This bit enables the external oscillator (OSCLCP). The UPOSC status bit in the
CPMUFLG register indicates when the oscillation is stable and OSCCLK can be selected as Bus Clock or source
of the COP or RTI. A loss of oscillation will lead to a clock monitor reset.
0 external Oscillator is disabled.
1 external Oscillator is enabled.Clock monitor is enabled.
Note: When starting up the external Oscillator (either by programming OSCEN bit to 1 or on exit from full stop
mode with OSCEN bit is already 1) the software must wait for a minimum time equivalent to the startup-
time of the external Oscillator t_UPOSC before entering Pseudo Stop Mode.
Oscillator Filter Bandwidth Bit
0 Oscillator filter bandwidth is narrow.
1 Oscillator filter bandwidth is wide.
Oscillator Filter Bits — When using the Oscillator a noise filter can be enabled, which filters noise from the
OSCCLK and detects if the OSCCLK is qualified or not (UPOSC status).
For example when using a 4MHz crystal and synthesizing a VCOCLK of 64 MHz, then OSCFILT must be set to
8 (64MHz / 4MHz = 16, 16 divided by 2 is 8).
0x00 Oscillator Filter disabled.
else Oscillator Filter enabled: the VCOCLK-to-OSCCLK frequency ratio divided by 2 must be written to
OSCFILT[4:0]
S12P-Family Reference Manual, Rev. 1.12
230
Freescale Semiconductor