MC9S12P128 Datasheet, PDF (46/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Device Overview MC9S12P-Family
Table 1-12. Interrupt Vector Locations (Sheet 3 of 3)
Vector Address⁽¹⁾
Interrupt Source
Vector base + $AE
to
Vector base + $90
Vector base + $8E
Port P interrupt
Vector base+ $8C
PWM emergency shutdown
Vector base + $8A
Low-voltage interrupt (LVI)
Vector base + $88
Autonomous periodical interrupt
(API)
Vector base + $86
High temperature interrupt
Vector base + $84
ATD compare interrupt
Vector base + $82
Vector base + $80
Spurious interrupt
1. 16 bits vector address based
CCR
Mask
Local Enable
Wake up Wakeup
from STOP from WAIT
Reserved
I bit PIEP (PIEP7,PIEP5-PIEP0)
Yes
Yes
I bit
PWMSDN (PWMIE)
No
Yes
I bit
CPMUCTRL (LVIE)
No
Yes
I bit
CPMUAPICTRL (APIE)
Yes
Yes
I bit
CPMUHTCL (HTIE)
I bit
ATDCTL2 (ACMPIE)
Reserved
—
None
No
Yes
Yes
Yes
-
-
1.11.3 Effects of Reset
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections
for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers.
1.11.3.1 Flash Configuration Reset Sequence Phase
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module section 13.6 Initialization.
1.11.3.2 Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.11.3.3 I/O Pins
Refer to the PIM section for reset configurations of all peripheral module ports.
1.11.3.4 Memory
The RAM arrays are not initialized out of reset.
S12P-Family Reference Manual, Rev. 1.12
46
Freescale Semiconductor