MC9S12P128 Datasheet, PDF (206/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE
Writing to this register clears the LOCK and UPOSC status bits.
If PLL has locked (LOCK=1)
fVCO = 2 × fREF × (SYNDIV + 1)
NOTE
f_VCO must be within the specified VCO frequency lock range. Bus
frequency f_bus must not exceed the specified maximum.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct
PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 7-1. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional
PLL (no locking and/or insufficient stability).
Table 7-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
32MHz <= f_VCO<= 48MHz
48MHz < f_VCO<= 64MHz
Reserved
Reserved
VCOFRQ[1:0]
00
01
10
11
7.3.2.2 S12CPMU Reference Divider Register (CPMUREFDIV)
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the
external Oscillator as reference.
0x0035
7
6
5
4
3
2
1
0
R
REFFRQ[1:0]
W
0
0
REFDIV[3:0]
Reset
0
0
0
0
1
1
1
1
Figure 7-5. S12CPMU Reference Divider Register (CPMUREFDIV)
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
S12P-Family Reference Manual, Rev. 1.12
206
Freescale Semiconductor