MC9S12P128 Datasheet, PDF (337/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Pulse-Width Modulator (PWM8B6CV1) Block Description
Table 10-5. PWMPRCLK Field Descriptions
Field
Description
6:5
Prescaler Select for Clock B — Clock B is 1 of two clock sources which can be used for channels 2 or 3. These
PCKB[2:0] three bits determine the rate of clock B, as shown in Table 10-6.
2:0
Prescaler Select for Clock A — Clock A is 1 of two clock sources which can be used for channels 0, 1, 4, or 5.
PCKA[2:0] These three bits determine the rate of clock A, as shown in Table 10-7.
PCKB2
0
0
0
0
1
1
1
1
Table 10-6. Clock B Prescaler Selects
PCKB1
0
0
1
1
0
0
1
1
PCKB0
0
1
0
1
0
1
0
1
Value of Clock B
Bus Clock
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Bus Clock / 16
Bus Clock / 32
Bus Clock / 64
Bus Clock / 128
PCKA2
0
0
0
0
1
1
1
1
Table 10-7. Clock A Prescaler Selects
PCKA1
0
0
1
1
0
0
1
1
PCKA0
0
1
0
1
0
1
0
1
Value of Clock A
Bus Clock
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Bus Clock / 16
Bus Clock / 32
Bus Clock / 64
Bus Clock / 128
10.3.2.5 PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains six control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a 1, the corresponding PWM output will be center
aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. Reference
Section 10.4.2.5, “Left Aligned Outputs,” and Section 10.4.2.6, “Center Aligned Outputs,” for a more
detailed description of the PWM output modes.
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
337