MC9S12P128 Datasheet, PDF (164/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12S Debug Module (S12SDBGV2)
Table 6-12. DBGCNT Field Descriptions
Field
7
TBF
5–0
CNT[5:0]
Description
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF
bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization.
Other system generated resets have no affect on this bit
This bit is also visible at DBGSR[7]
Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer.
Table 6-13 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.
When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-
trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register
is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset occur
during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer
entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace
buffer.
Table 6-13. CNT Decoding Table
TBF
CNT[5:0]
0
000000
0
000001
000010
000100
000110
..
111111
1
000000
1
000001
..
..
111110
Description
No data valid
1 line valid
2 lines valid
4 lines valid
6 lines valid
..
63 lines valid
64 lines valid; if using Begin trigger alignment,
ARM bit will be cleared and the tracing session ends.
64 lines valid,
oldest data has been overwritten by most recent data
6.3.2.7 Debug State Control Registers
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
next state for the state sequencer following a match. The three debug state control registers are located at
the same address in the register address map (0x0027). Each register can be accessed using the COMRV
bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register
(DBGMFR).
Table 6-14. State Control Register Access Encoding
COMRV
00
01
10
11
Visible State Control Register
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
S12P-Family Reference Manual, Rev. 1.12
164
Freescale Semiconductor