MC9S12P128 Datasheet, PDF (557/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Detailed Register Address Map
MSCAN Foreground Receive and Transmit Buffer Layout
Address Name
Extended ID R
0xXXX0 Standard ID R
CANxRIDR0 W
Extended ID R
0xXXX1 Standard ID R
CANxRIDR1 W
Extended ID R
0xXXX2 Standard ID R
CANxRIDR2 W
Extended ID R
0xXXX3 Standard ID R
CANxRIDR3 W
0xXXX4- CANxRDSR0- R
0xXXXB CANxRDSR7 W
R
0xXXXC CANRxDLR
W
R
0xXXXD Reserved
W
R
0xXXXE CANxRTSRH
W
R
0xXXXF CANxRTSRL
W
Extended ID R
CANxTIDR0 W
0xXX10
Standard ID R
W
Extended ID R
0xXX0x ^{CANxTIDR1 W}
XX10 Standard ID R
W
Extended ID R
CANxTIDR2 W
0xXX12
Standard ID R
W
Extended ID R
CANxTIDR3 W
0xXX13
Standard ID R
W
0xXX14- CANxTDSR0– R
0xXX1B CANxTDSR7 W
R
0xXX1C CANxTDLR
W
R
0xXX1D CANxTTBPR
W
Bit 7
ID28
ID10
ID20
ID2
ID14
ID6
DB7
TSR15
TSR7
ID28
ID10
ID20
ID2
ID14
ID6
DB7
PRIO7
Bit 6
ID27
ID9
ID19
ID1
ID13
ID5
DB6
TSR14
TSR6
ID27
ID9
ID19
ID1
ID13
ID5
DB6
PRIO6
Bit 5
ID26
ID8
ID18
ID0
ID12
ID4
DB5
TSR13
TSR5
ID26
ID8
ID18
ID0
ID12
ID4
DB5
PRIO5
Bit 4
ID25
ID7
SRR=1
RTR
ID11
ID3
DB4
TSR12
TSR4
ID25
ID7
SRR=1
RTR
ID11
ID3
DB4
PRIO4
Bit 3
ID24
ID6
IDE=1
IDE=0
ID10
ID2
DB3
DLC3
TSR11
TSR3
ID24
ID6
IDE=1
IDE=0
ID10
ID2
DB3
DLC3
PRIO3
Bit 2
ID23
ID5
ID17
ID9
ID1
DB2
DLC2
TSR10
TSR2
ID23
ID5
ID17
ID9
ID1
DB2
DLC2
PRIO2
Bit 1
ID22
ID4
ID16
ID8
ID0
DB1
DLC1
TSR9
TSR1
ID22
ID4
ID16
ID8
ID0
DB1
DLC1
PRIO1
Bit 0
ID21
ID3
ID15
ID7
RTR
DB0
DLC0
TSR8
TSR0
ID21
ID3
ID15
ID7
RTR
DB0
DLC0
PRIO0
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
557