MC9S12P128 Datasheet, PDF (18/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Device Overview MC9S12P-Family
1.2.1 MC9S12P Family Comparison
Table 1 provides a summary of different members of the MC9S12P family and their proposed features.
This information is intended to provide an understanding of the range of functionality offered by this
microcontroller family.
Table 1. MC9S12P Family
Feature
MC9S12P32
MC9S12P64
MC9S12P96
MC9S12P128
CPU
CPU12-V1
Flash memory (ECC)
Data flash (ECC)
RAM
MSCAN
SCI
SPI
Timer
PWM
ADC
32 Kbytes
2 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
4 Kbytes
4 Kbytes
6 Kbytes
1
1
1
8 ch x 16-bit
6 ch x 8-bit
10 ch x 12-bit
Frequency modulated PLL
Yes
External oscillator
Yes
(4 – 16 MHz Pierce with
loop control)
Internal 1 MHz RC
Yes
oscillator
Supply voltage
Execution speed
3.15 V – 5.5 V
Static⁽¹⁾ – 32 MHz
Package
80 QFP, 64 LQFP, 48 QFN
1. P or D Flash erasing or programming requires a minimum bus frequency of 1MHz
1.2.2 Chip-Level Features
On-chip modules available within the family include the following features:
• S12 CPU core
• Up to 128 Kbyte on-chip flash with ECC
• 4 Kbyte data flash with ECC
• Up to 6 Kbyte on-chip SRAM
• Phase locked loop (IPLL) frequency multiplier with internal filter
• 4–16 MHz amplitude controlled Pierce oscillator
• 1 MHz internal RC oscillator
• Timer module (TIM) supporting input/output channels that provide a range of 16-bit input capture,
output compare, counter, and pulse accumulator functions
S12P-Family Reference Manual, Rev. 1.12
18
Freescale Semiconductor