MC9S12P128 Datasheet, PDF (218/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
0x003E
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-14. Reserved Register (CPMUTEST1)
Read: Anytime
Write: Only in special mode
7.3.2.12 S12CPMU COP Timer Arm/Reset Register (CPUARMCOP)
This register is used to restart the COP time-out period.
0x003F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0
0
0
0
0
0
0
0
Figure 7-15. S12CPMU CPMUARMCOP Register
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the
sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset.
Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done
in the last 25% of the selected time-out period; writing any value in the first 75% of the selected
period will cause a COP reset.
7.3.2.13 High Temperature Control Register (CPMUHTCTL)
The CPMUHTCTL register configures the temperature sense features.
S12P-Family Reference Manual, Rev. 1.12
218
Freescale Semiconductor