MC9S12P128 Datasheet, PDF (133/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Background Debug Module (S12SBDMV1)
In stop mode the BDM clocks are stopped. When BDM clocks are disabled and stop mode is exited, the
BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in
progress and disable the ACK function). The BDM is now ready to receive a new command.
5.1.3 Block Diagram
A block diagram of the BDM is shown in Figure 5-1.
Host
System _BKGD
Serial
Interface
Register Block
Data
Control
16-Bit Shift Register
TRACE
BDMACT
Instruction Code
and
Execution
Bus Interface
and
Control Logic
Address
Data
Control
Clocks
ENBDM
SDV
UNSEC
BDMSTS
Register
Standard BDM Firmware
LOOKUP TABLE
Secured BDM Firmware
LOOKUP TABLE
Figure 5-1. BDM Block Diagram
5.2 External Signal Description
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode. The communication rate of this pin is based on the the settings for the VCO clock
(CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8. After reset the
BDM clock is based on the reset values of the CPMUSYNR register (4 MHz). When modifying the VCO
clock please make sure that the communication rate is adapted accordingly and a communication time-out
(BDM soft reset) has occurred.
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
133