MC9S12P128 Datasheet, PDF (231/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.3.2.22 S12CPMU Protection Register (CPMUPROT)
This register is for protecting the clock configuration registers CPMUSYNR, CPMUREFDIV, CPMUPLL,
CPMUIRCTRIMH/L and CPMUOSC from accidental overwrite.
0x02FB
7
R
0
W
Reset
0
Read: Anytime
Write: Anytime
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-30. S12CPMU Protection Register (CPMUPROT)
0
PROT
0
Field
0
Description
Clock Configuration Registers Protection Bit — This bit is to protect the following clock configuration registers
from accidental overwrite: CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L and
CPMUOSC.
Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit.
0 Protection of clock configuration registers is disabled.
1 Protection of clock configuration registers is enabled. CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL,
CPMUIRCTRIMH/L and CPMUOSC are not writable.
7.3.2.23
Reserved Register CPMUTEST2
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
mode can alter the S12CPMU’s functionality.
0x02FC
7
6
5
4
3
2
1
R
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-31. Reserved Register CPMUTEST2
Freescale Semiconductor
S12P-Family Reference Manual, Rev. 1.12
0
0
0
231