MC9S12P128 Datasheet, PDF (203/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
NOTE
Freescale recommends an evaluation of the application board and chosen
resonator or crystal by the resonator or crystal supplier.
Loop controlled circuit is not suited for overtone resonators and crystals.
7.2.3 TEMPSENSE — temperature sensor output voltage
Depending on the VSEL value either the voltage level generated by the temperature sensor or the VREG
bandgap voltage is driven to a special channel of the ATD Converter. See device level specification for
connectivity.
7.2.4 VDDR — Regulator Power Input Pin
VDDR is the power input of IVREG. All currents sourced into the regulator loads flow through this pin.
A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSS can
smooth ripple on VDDR.
7.2.5 VDDA, VSSA — Regulator Reference Supply Pins
VDDA/VSSA_, which are relatively quiet, are used to supply the analog parts of the regulator. Internal
precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100
nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of this supply.
7.2.6 VSS, VSSPLL— Ground Pins
VSS and VSSPLL must be grounded.
7.2.7 VDDX, VSSX— Pad Supply Pins
This supply domain is monitored by the Low Voltage Reset circuit.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDX and VSSX can further
improve the quality of this supply.
7.2.8 API_EXTCLK — API external clock output pin
This pin provides the signal selected via APIES and is enabled with APIEA bit. See device specification
to which pin it connects.
7.3 Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12CPMU.
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
203