MC9S12P128 Datasheet, PDF (200/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
The voltage regulator is in reduced power mode (RPM).
The API is available.
The Phase Locked Loop (PLL) is off.
The Internal Reference Clock (IRC1M) is off.
Core Clock, Bus Clock and BDM Clock are stopped.
Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full
Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1).
• Full Stop Mode
The oscillator (OSCLCP) is disabled.
After wake from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK
(PLLSEL=1). COP and RTI are running on IRCCLK (COPOSCSEL=0, RTIOSCSEL=0).
• Pseudo Stop Mode
The oscillator (OSCLCP) continues torun. If the respective enable bits are set the COP and RTI
will continue to run.
The clock configuration bits PLLSEL, COPOSCSEL, RTIOSCSEL are unchanged.
NOTE
When starting up the external Oscillator (either by programming OSCEN
bit to 1 or on exit from full stop mode with OSCEN bit is already 1) the
software must wait for a minimum time equivalent to the startup-time of the
external Oscillator t_UPOSC before entering Pseudo Stop Mode.
7.1.3 Block Diagram
Figure 7-1 shows a block diagram of the S12CPMU.
S12P-Family Reference Manual, Rev. 1.12
200
Freescale Semiconductor