MC9S12P128 Datasheet, PDF (212/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
0x003A
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
FM1
FM0
W
Reset
0
0
0
0
0
0
0
0
Figure 7-10. S12CPMU PLL Control Register (CPMUPLL)
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
NOTE
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
NOTE
When using the oscillator filter, that is in the CPMUOSC register OSCEN=1
and OSCFILT[4:0] is not 00000, then the frequency modulation must be
turned off (FM1=0, FM0=0).
Table 7-6. CPMUPLL Field Descriptions
Field
Description
5, 4
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
FM1, FM0 is to reduce noise emission. The modulation frequency is f_ref divided by 16. See Table 7-7 for coding.
Table 7-7. FM Amplitude selection
FM1
0
0
1
1
FM0
0
1
0
1
FM Amplitude /
f_VCO Variation
FM off
±1%
±2%
±4%
S12P-Family Reference Manual, Rev. 1.12
212
Freescale Semiconductor