MC9S12P128 Datasheet, PDF (201/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
MMC
Illegal Address Access
VDDR
VSSPLL
VSS
VDD, VDDPLL, VDDF
(core supplies)
Low Voltage Detect VDDA
Low Voltage Detect VDDX
ILAF
LVDS
LVIE ^{Low Voltage Interrupt}
VDDX
VSSX
Voltage
Regulator
Power-On Detect
LVRF
COP time out
S12CPMU
VDDA ^{3.13 to 5.5V}
PORF
VSSA
Power-On Reset
RESET
Reset
System Reset
Clock
Monitor
monitor fail
Generator
UPOSC _{UPOSC=0 sets PLLSEL bit}
Oscillator status Interrupt
OSCIE
Loop
EXTAL Controlled
Pierce
Oscillator
XTAL (OSCLCP)
adaptive
spike
filter
OSCCLK
OSCFILT[4:0]
& CAN_OSCCLK
(to MSCAN)
PLLSEL
4MHz-16MHz _{REFDIV[3:0] IRCTRIM[9:0]}
POSTDIV[4:0]
PSTP
Reference
Divider
Internal
Reference
Clock
(IRC1M)
Post
Divider
1,2,..32
divide
by 4
OSCE
Lock
detect
VCOFRQ[1:0]
REFCLK
FBCLK
Phase
locked
Loop with
internal
Filter (PLL)
VCOCLK
LOCK
REFFRQ[1:0]
PLLCLK
Core Clock
divide Bus Clock
by 2 _IRCCLK
(to LCD)
divide
by 8
BDM Clock
HTDS HTIE ^{HT Interrupt}
High
Temperature
Sense
LOCKIE ^{PLL Lock Interrupt}
UPOSC
UPOSC=0 clears
Divide by
2*(SYNDIV+1)
SYNDIV[5:0]
Bus Clock
RC ^ACLK
Osc.
Autonomous
Periodic
API_EXTCLK
Interrupt (API)
APICLK
APIE
RTIE
API Interrupt
RTI Interrupt
IRCCLK
OSCCLK
COPCLK
COP
Watchdog
COP time out
to Reset
Generator
IRCCLK
OSCCLK
Real Time
RTICLK _{Interrupt (RTI)}
COPOSCSEL _PCE CPMUCOP
RTIOSCSEL _PRE CPMURTI
Figure 7-1. Block diagram of S12CPMU
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
201