MC9S12P128 Datasheet, PDF (242/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
A write to the CPMURTI register restarts the RTI time-out period.
7.6.1.2 PLL Lock Interrupt
The S12CPMU generates a PLL Lock interrupt when the lock condition (LOCK status bit) of the PLL
changes, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled
by setting the LOCKIE bit to zero. The PLL Lock interrupt flag (LOCKIF) is set to1 when the lock
condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
7.6.1.3 Oscillator Status Interrupt
The Oscillator Filter has 2 different tasks:
1. It filters spikes.
2. It qualifies the oscillation.
When the OSCE bit is 0, then UPOSC stays 0. When OSCEN=1 and OSCFILT = 0, then the filter is
transparent and no spikes are filtered. The UPOSC bit is then set after the LOCK bit is set.
Upon detection of a status change (UPOSC), that is either a unqualified oscillation becomes qualified or
vice versa the OSCIF flag is set. Going into full stop mode or disabling the oscillator can also cause a status
change of UPOSC.
Also, since the oscillator filter is based on the PLL clock, any change in PLL configuration or any other
event which causes the PLL lock status to be cleared leads to a loss of the oscillator status information as
well (UPOSC=0).
Oscillator status change interrupts are locally enabled with the OSCIE bit.
NOTE
Losing the oscillator status (UPOSC=0) affects the clock configuration of
the system¹. This needs to be dealt with in application software.
7.6.1.4 Low-Voltage Interrupt (LVI)
In FPM the input voltage V_DDA is monitored. Whenever V_DDA drops below level V_LVIA, the status bit
LVDS is set to 1. On the other hand, LVDS is reset to 0 when V_DDA rises above level V_LVID. An interrupt,
indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE
= 1.
7.6.1.5 HTI - High Temperature Interrupt
In FPM the junction temperature T_J is monitored. Whenever T_J exceeds level T_HTIA the status bit HTDS
is set to 1. Vice versa, HTDS is reset to 0 when T_J get below level T_HTID. An interrupt, indicated by flag
HTIF = 1, is triggered by any change of the status bit HTDS, if interrupt enable bit HTIE = 1.
1. For details please refer to “7.4.6 System Clock Configurations”
S12P-Family Reference Manual, Rev. 1.12
242
Freescale Semiconductor