MC9S12P128 Datasheet, PDF (226/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
0x02F8
15
14
13
12
11
10
R
TCTRIM[3:0]
W
0
0
9
8
IRCTRIM[9:8]
Reset
F
F
F
F
0
0
F
F
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency f_{IRC1M_TRIM}.
Figure 7-24. S12CPMU IRC1M Trim High Register (CPMUIRCTRIMH)
0x02F9
7
6
5
4
3
2
1
0
R
IRCTRIM[7:0]
W
Reset
F
F
F
F
F
F
F
F
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency f_{IRC1M_TRIM}.
Figure 7-25. S12CPMU IRC1M Trim Low Register (CPMUIRCTRIML)
Read: Anytime
Write: If PROT=0 (CPMUPROT register), then write anytime. Else write has no effect
NOTE
Writes to these registers while PLLSEL=1 clears the LOCK and UPOSC
status bits.
S12P-Family Reference Manual, Rev. 1.12
226
Freescale Semiconductor