MC9S12P128 Datasheet, PDF (135/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Background Debug Module (S12SBDMV1)
Global
Address
0x3_FF06
Register
Name
BDMCCR R
W
Bit 7
CCR7
0x3_FF07 Reserved R
0
W
0x3_FF08 BDMPPR R
BPAE
W
0x3_FF09 Reserved R
0
W
0x3_FF0A Reserved R
0
W
0x3_FF0B Reserved R
0
W
6
CCR6
0
0
0
0
0
5
CCR5
0
0
0
0
0
4
CCR4
0
0
0
0
0
3
CCR3
0
BPP3
0
0
0
2
CCR2
0
BPP2
0
0
0
1
CCR1
0
BPP1
0
0
0
Bit 0
CCR0
0
BPP0
0
0
0
= Unimplemented, Reserved
= Implemented (do not alter)
X
= Indeterminate
0
= Always read zero
Figure 5-2. BDM Register Summary (continued)
5.3.2.1 BDM Status Register (BDMSTS)
Register Global Address 0x3_FF01
7
R
ENBDM
W
Reset
Special Single-Chip Mode 0⁽¹⁾
All Other Modes
0
6
5
BDMACT
0
4
SDV
1
0
0
0
0
0
= Unimplemented, Reserved
3
2
1
0
TRACE
0
UNSEC
0
0
0
0⁽²⁾
0
0
0
0
0
= Implemented (do not alter)
0
= Always read zero
1. ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but
fully erased (Flash). This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully
transmitted and executed.
2. UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,
else it is 0 and can only be read if not secure (see also bit description).
Figure 5-3. BDM Status Register (BDMSTS)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured, but subject to the following:
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
135