MC9S12P128 Datasheet, PDF (322/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Analog-to-Digital Converter (ADC12B10CRev 00.05) Block Description
9.3.2.12.1 Left Justified Result Data (DJM=0)
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-14. Left justified ATD conversion result register (ATDDRn)
9.3.2.12.2 Right Justified Result Data (DJM=1)
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0
0
0
0
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi1 1 Bit 0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-15. Right justified ATD conversion result register (ATDDRn)
Table 9-21 shows how depending on the A/D resolution the conversion result is transferred to the ATD
result registers. Compare is always done using all 12 bits of both the conversion result and the compare
value in ATDDRn.
Table 9-21. Conversion result mapping to ATDDRn
A/D
resolution
DJM
conversion result mapping to
ATDDRn
8-bit data 0
8-bit data 1
10-bit data 0
10-bit data 1
12-bit data X
Bit[11:4] = result, Bit[3:0]=0000
Bit[7:0] = result, Bit[11:8]=0000
Bit[11:2] = result, Bit[1:0]=00
Bit[9:0] = result, Bit[11:10]=00
Bit[11:0] = result
9.4 Functional Description
The ADC12B10C is structured into an analog sub-block and a digital sub-block.
S12P-Family Reference Manual, Rev. 1.12
322
Freescale Semiconductor