MC9S12P128 Datasheet, PDF (254/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Register
Name
0x000E
CANRXERR
Bit 7
6
5
4
3
2
1
Bit 0
R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
W
0x000F
CANTXERR
R TXERR7
W
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
0x0010–0x0013 R
CANIDAR0–3 _W ^AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
0x0014–0x0017 R
CANIDMRx
W
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
0x0018–0x001B R
CANIDAR4–7 _W ^AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
0x001C–0x001F R
CANIDMR4–7 _W
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
0x0020–0x002F R
CANRXFG
W
See Section 8.3.3, “Programmer’s Model of Message Storage”
0x0030–0x003F R
CANTXFG
W
See Section 8.3.3, “Programmer’s Model of Message Storage”
= Unimplemented or Reserved
Figure 8-3. MSCAN Register Summary (continued)
8.3.2 Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated figure number. Details of register bit and field
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
8.3.2.1 MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
S12P-Family Reference Manual, Rev. 1.12
254
Freescale Semiconductor