MC9S12P128 Datasheet, PDF (205/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
Addres
s
Name
R
0x02F5 CPMUAPIRL
W
0x02F6
RESERVED
CPMUTEST3
R
W
R
0x02F7 CPMUHTTR
W
0x02F8
CPMU
IRCTRIMH
R
W
0x02F9
CPMU
IRCTRIML
R
W
R
0x02FA CPMUOSC
W
R
0x02FB CPMUPROT
W
0x02FC
RESERVED
CPMUTEST2
R
W
Bit 7
APIR7
0
HTOE
OSCE
0
0
6
APIR6
0
5
APIR5
0
0
0
TCTRIM[3:0]
0
OSCBW
0
0
0
0
4
3
2
APIR4
0
APIR3
0
APIR2
0
1
APIR1
0
Bit 0
APIR0
0
0
HTTR3 HTTR2 HTTR1 HTTR0
0
0
IRCTRIM[9:8]
IRCTRIM[7:0]
OSCFILT[4:0]
0
0
0
0
PROT
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-3. CPMU Register Summary
7.3.2 Register Descriptions
This section describes all the S12CPMU registers and their individual bits.
Address order is as listed in Figure 7-3.
7.3.2.1 S12CPMU Synthesizer Register (CPMUSYNR)
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency
range.
0x0034
7
6
5
4
3
2
1
0
R
VCOFRQ[1:0]
W
SYNDIV[5:0]
Reset
0
1
0
1
1
1
1
1
Figure 7-4. S12CPMU Synthesizer Register (CPMUSYNR)
Read: Anytime
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
205