MC9S12P128 Datasheet, PDF (335/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Pulse-Width Modulator (PWM8B6CV1) Block Description
Table 10-3. PWMPOL Field Descriptions (continued)
Field
3
PPOL3
2
PPOL2
1
PPOL1
0
PPOL0
Description
Pulse Width Channel 3 Polarity
0 PWM channel 3 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 3 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 2 Polarity
0 PWM channel 2 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 2 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 1 Polarity
0 PWM channel 1 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 1 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 0 Polarity
0 PWM channel 0 output is low at the beginning of the period, then goes high when the duty count is reached
1 PWM channel 0 output is high at the beginning of the period, then goes low when the duty count is reached.
10.3.2.3 PWM Clock Select Register (PWMCLK)
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described
below.
Module Base + 0x0002
7
R
0
W
6
5
4
3
2
1
0
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-5. PWM Clock Select Register (PWMCLK)
Read: anytime
Write: anytime
NOTE
Register bits PCLK0 to PCLK5 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
0
PCLK0
0
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
335