MC9S12P128 Datasheet, PDF (207/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
NOTE
Write to this register clears the LOCK and UPOSC status bits.
If OSCLCP is enabled (OSCE=1)
If OSCLCP is disabled (OSCE=0)
f _REF = ₍---_R----_E----_F-^f--^OD-----^SI--_V-^C-----₊-----₁---₎-
fREF = fIRC1M
The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For
correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in Table 7-2.
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= f_REF <=
2MHz range. The bits cans still be written but will have no effect on the PLL filter configuration.
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking
and/or insufficient stability).
Table 7-2. Reference Clock Frequency Selection if OSC_LCP is enabled
REFCLK Frequency Ranges
(OSCE=1)
1MHz <= f_REF <= 2MHz
2MHz < f_REF <= 6MHz
6MHz < f_REF <= 12MHz
f_REF >12MHz
REFFRQ[1:0]
00
01
10
11
7.3.2.3 S12CPMU Post Divider Register (CPMUPOSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
0x0036
7
6
5
4
3
2
1
0
R
0
0
0
W
POSTDIV[4:0]
Reset
0
0
0
0
0
0
1
1
= Unimplemented or Reserved
Figure 7-6. S12CPMU Post Divider Register (CPMUPOSTDIV)
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
207