MC9S12P128 Datasheet, PDF (521/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Electrical Characteristics
NOTE
All values shown in Table A-19 are preliminary and subject to further
characterization.
Table A-19. NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol Min Typ Max Unit
Program Flash Arrays
1 C Data retention at an average junction temperature of T_Javg =
85°C⁽¹⁾ after up to 10,000 program/erase cycles
t_NVMRET
2 C Program Flash number of program/erase cycles
(-40°C ≤ tj ≤ 150°C)
n_FLPE
20 100⁽²⁾ —
10K 100K⁽³⁾ —
Years
Cycles
Data Flash Array
3 C Data retention at an average junction temperature of T_Javg =
85°C¹ after up to 50,000 program/erase cycles
t_NVMRET
5
100²
— Years
4 C Data retention at an average junction temperature of T_Javg =
85°C¹ after up to 10,000 program/erase cycles
t_NVMRET
10
100²
— Years
5 C Data retention at an average junction temperature of T_Javg =
85°C¹ after less than 100 program/erase cycles
t_NVMRET
20
100²
— Years
6 C Data Flash number of program/erase cycles (-40°C ≤ tj ≤ 150°C) n_FLPE
50K 500K³ — Cycles
1. T_Javg does not exceed 85°C in a typical temperature profile over the lifetime of a consumer, industrial or automotive
application.
2. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please
refer to Engineering Bulletin EB618
3. Spec table quotes typical endurance evaluated at 25°C for this product family. For additional information on how Freescale
defines Typical Endurance, please refer to Engineering Bulletin EB619.
A.4 Phase Locked Loop
A.4.1 Jitter Definitions
With each transition of the feedback clock, the deviation from the reference clock is measured and input
voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes
in the VCOCLK frequency. Noise, voltage, temperature and other factors cause slight variations in the
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
illustrated in Figure A-2.
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
521