MC9S12P128 Datasheet, PDF(224/564 Page) Freescale Semiconductor, Inc – S12 Microcontrollers

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MC9S12P128 Datasheet, PDF (224/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

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S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description

Table 7-19. Selectable Autonomous Periodical Interrupt Periods (continued)

APICLK

APIR[15:0]

0

0001

0

0002

0

0003

0

0004

0

0005

0

.....

0

FFFD

0

FFFE

0

FFFF

1

0000

1

0001

1

0002

1

0003

1

0004

1

0005

1

.....

1

FFFD

1

FFFE

1

FFFF

1. When fACLK is trimmed to 10KHz.

Selected Period

0.4 ms1

0.6 ms1

0.8 ms1

1.0 ms1

1.2 ms1

.....

13106.8 ms1

13107.0 ms1

13107.2 ms1

2 * Bus Clock period

4 * Bus Clock period

6 * Bus Clock period

8 * Bus Clock period

10 * Bus Clock period

12 * Bus Clock period

.....

131068 * Bus Clock period

131070 * Bus Clock period

131072 * Bus Clock period

7.3.2.18

Reserved Register CPMUTEST3

NOTE

This reserved register is designed for factory test purposes only, and is not

intended for general user access. Writing to this register when in special

mode can alter the S12CPMUâs functionality.

0x02F6

7

R

0

W

Reset

0

Read: Anytime

6

5

4

3

2

0

0

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 7-23. Reserved Register (CPMUTEST3)

S12P-Family Reference Manual, Rev. 1.12

224

1

0

0

0

0

0

Freescale Semiconductor

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