MC9S12P128 Datasheet, PDF (55/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12PPIMV1)
Table 2-2. Block Memory Map (continued)
Port
Offset or
Address
Register
Access Reset Value Section/Page
J 0x0268 PTJ—Port J Data Register
R/W
0x0269 PTIJ—Port J Input Register
R
0x026A DDRJ—Port J Data Direction Register
R/W
0x026B RDRJ—Port J Reduced Drive Register
R/W
0x026C PERJ—Port J Pull Device Enable Register
R/W
0x026D PPSJ—Port J Polarity Select Register
R/W
0x026E PIEJ—Port J Interrupt Enable Register
R/W
0x026F PIFJ—Port J Interrupt Flag Register
R/W
AD 0x0270 PT0AD—Port AD Data Register
R
0x0271 PT1AD—Port AD Data Register
R/W
0x0272 DDR0AD—Port AD Data Direction Register
R
0x0273 DDR1AD—Port AD Data Direction Register
R/W
0x0274 RDR0AD—Port AD Reduced Drive Register
R
0x0275 RDR1AD—Port AD Reduced Drive Register
R/W
0x0276 PER0AD—Port AD Pull Up Enable Register
R
0x0277 PER1AD—Port AD Pull Up Enable Register
R/W
0x0278 PIM Reserved
R
:
0x027F
1. Write access not applicable for one or more register bits. Refer to register description.
2. Refer to device memory map to determine related module.
3. Mode dependent.
4. Read always returns logic level on pins.
0x00
4
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
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Register
Name
Bit 7
6
5
4
0x0000 R
PORTA _W
PA7
PA6
PA5
PA4
0x0001 R
PORTB _W
PB7
PB6
PB5
PB4
0x0002 R
DDRA _W ^DDRA7
DDRA6
DDRA5
DDRA4
0x0003 R
DDRB _W ^DDRB7
DDRB6
DDRB5
DDRB4
= Unimplemented or Reserved
3
PA3
PB3
DDRA3
DDRB3
2
PA2
PB2
DDRA2
DDRB2
1
PA1
PB1
DDRA1
DDRB1
Bit 0
PA0
PB0
DDRA0
DDRB0
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
55