MC9S12P128 Datasheet, PDF (479/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Timer Module (TIM16B8CV2) Block Description
Read: Anytime but will always return 0x0000 (1 state is transient)
Write: Anytime
Table 14-3. CFORC Field Descriptions
Field
Description
7:0
FOC[7:0]
Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A successful channel 7 output compare overrides any channel 6:0 compares. If forced output compare on
any channel occurs at the same time as the successful output compare then forced output compare action
will take precedence and interrupt flag won’t get set.
14.3.2.3 Output Compare 7 Mask Register (OC7M)
Module Base + 0x0002
R
W
Reset
7
OC7M7
0
6
OC7M6
5
OC7M5
4
OC7M4
3
OC7M3
2
OC7M2
0
0
0
0
0
Figure 14-8. Output Compare 7 Mask Register (OC7M)
1
OC7M1
0
0
OC7M0
0
Read: Anytime
Write: Anytime
Table 14-4. OC7M Field Descriptions
Field
Description
7:0
OC7M[7:0]
Output Compare 7 Mask — Setting the OC7Mx (x ranges from 0 to 6) will set the corresponding port to be an
output port when the corresponding TIOSx (x ranges from 0 to 6) bit is set to be an output compare and the
corresponding OCPDx (x ranges from 0 to 6) bit is set to zero to enable the timer port.
A successful channel 7 output compare overrides any channel 6:0 compares. For each OC7M bit that is set, the
output compare action reflects the corresponding OC7D bit.
14.3.2.4 Output Compare 7 Data Register (OC7D)
Module Base + 0x0003
R
W
Reset
7
OC7D7
0
6
OC7D6
5
OC7D5
4
OC7D4
3
OC7D3
2
OC7D2
0
0
0
0
0
Figure 14-9. Output Compare 7 Data Register (OC7D)
1
OC7D1
0
0
OC7D0
0
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
479