MC9S12P128 Datasheet, PDF (225/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Write: Only in special mode
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.3.2.19 High Temperature Trimming Register (CPMUHTTR)
The CPMUHTTR register configures the trimming of the S12CPMU temperature sense.
0x02F7
7
6
5
4
3
2
1
0
R
0
0
0
HTOE
HTTR3
HTTR2
HTTR1
HTTR0
W
Reset
0
0
0
0
F
F
F
F
After de-assert of System Reset a trim value is automatically loaded from the Flash memory. See Device specification for
details.
= Unimplemented or Reserved
Read: Anytime
Write: Anytime
Field
Description
7
HTOE
3–0
HTTR[3:0]
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled.
0 The temperature sense offset is disabled. HTTR[3:0] bits don’t care.
1 The temperature sense offset is enabled. HTTR[3:0] select the temperature offset.
High Temperature Trimming Bits — See Table 1-27 for trimming effects.
Bit
HTTR[3]
HTTR[2]
HTTR[1]
HTTR[0]
Trimming Effect
Increases V_HT twice of HTTR[2]
Increases V_HT twice of HTTR[1]
Increases V_HT twice of HTTR[0]
Increases V_HT (to compensate Temperature Offset)
7.3.2.20 S12CPMU IRC1M Trim Registers (CPMUIRCTRIMH / CPMUIRCTRIML)
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
225