MC9S12P128 Datasheet, PDF (50/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12PPIMV1)
2.1.2 Features
The Port Integration Module includes these distinctive registers:
• Data registers and data direction registers for Ports A, B, E, T, S, M, P, J and AD when used as
general purpose I/O
• Control registers to enable/disable pull devices and select pull-ups/pull-downs on Ports T, S, M, P
and J on per-pin basis
• Control registers to enable/disable pull-up devices on Port AD on per-pin basis
• Single control register to enable/disable pull-ups on Ports A, B, and E, on per-port basis and on
BKGD pin
• Control registers to enable/disable reduced output drive on Ports T, S, M, P, J and AD on per-pin
basis
• Single control register to enable/disable reduced output drive on Ports A, B, and E on per-port basis
• Control registers to enable/disable open-drain (wired-or) mode on Ports S and M
• Interrupt flag register for pin interrupts on Ports P and J
• Control register to configure IRQ pin operation
• Routing register to support module port relocation
• Free-running clock outputs
A standard port pin has the following minimum features:
• Input/output selection
• 5V output drive with two selectable drive strengths
• 5V digital and analog input
• Input with selectable pull-up or pull-down device
Optional features supported on dedicated pins:
• Open drain for wired-or connections
• Interrupt inputs with glitch filtering
2.2 External Signal Description
This section lists and describes the signals that do connect off-chip.
Table 2-1 shows all the pins and their functions that are controlled by the Port Integration Module.
NOTE
If there is more than one function associated with a pin, the priority is
indicated by the position in the table from top (highest priority) to bottom
(lowest priority).
S12P-Family Reference Manual, Rev. 1.12
50
Freescale Semiconductor