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| MC9S12P128 Datasheet, PDF (215/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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RTR[3:0]
0101 (÷6)
0110 (÷7)
0111 (÷8)
1000 (÷9)
1001 (÷10)
1010 (÷11)
1011 (÷12)
1100 (÷13)
1101 (÷14)
1110 (÷15)
1111 (÷16)
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
Table 7-10. RTI Frequency Divide Rates for RTDEC=1
000
(1x103)
6x103
7x103
8x103
9x103
10 x103
11 x103
12x103
13x103
14x103
15x103
16x103
001
(2x103)
12x103
14x103
16x103
18x103
20x103
22x103
24x103
26x103
28x103
30x103
32x103
010
(5x103)
30x103
35x103
40x103
45x103
50x103
55x103
60x103
65x103
70x103
75x103
80x103
RTR[6:4] =
011
(10x103)
60x103
70x103
80x103
90x103
100x103
110x103
120x103
130x103
140x103
150x103
160x103
100
(20x103)
120x103
140x103
160x103
180x103
200x103
220x103
240x103
260x103
280x103
300x103
320x103
101
(50x103)
300x103
350x103
400x103
450x103
500x103
550x103
600x103
650x103
700x103
750x103
800x103
110
(100x103)
600x103
700x103
800x103
900x103
1x106
1.1x106
1.2x106
1.3x106
1.4x106
1.5x106
1.6x106
111
(200x103)
1.2x106
1.4x106
1.6x106
1.8x106
2x106
2.2x106
2.4x106
2.6x106
2.8x106
3x106
3.2x106
7.3.2.9 S12CPMU COP Control Register (CPMUCOP)
This register controls the COP (Computer Operating Properly) watchdog.
The clock source for the COP is either IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL bit. In Stop Mode with PSTP=1, COPOSCSEL=1 and PCE=1 the COP continues to run,
else the COP counter halts in Stop Mode.
0x003C
7
6
5
4
R
0
0
WCOP
RSBCK
W
WRTMASK
3
2
1
0
0
CR2
CR1
CR0
Reset
F
0
0
0
0
F
F
F
After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for
details.
= Unimplemented or Reserved
Figure 7-12. S12CPMU COP Control Register (CPMUCOP)
Read: Anytime
Write:
1. RSBCK: anytime in special mode; write to â1â but not to â0â in normal mode
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
215
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