MC9S12P128 Datasheet, PDF (199/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.1.2 Modes of Operation
This subsection lists and briefly describes all operating modes supported by the S12CPMU.
7.1.2.1 Run Mode
The voltage regulator is in full performance mode (FPM).
The Phase Locked Loop (PLL) is on.
The Internal Reference Clock (IRC1M) is on.
The API is available.
• PLL Engaged Internal (PEI)
— This is the default mode after System Reset and Power-On Reset.
— The Bus Clock is based on the PLL Clock.
— After reset the PLL is configured for 64MHz VCOCLK operation
Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 16MHz and Bus Clock is
8MHz.
The PLL can be re-configured for other bus frequencies.
— The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M
• PLL Engaged External (PEE)
— The Bus Clock is based on the PLL Clock.
— This mode can be entered from default mode PEI by performing the following steps:
– Configure the PLL for desired bus frequency.
– Program the reference divider (REFDIV[3:0] bits) to divide down Oscillator frequency if
necessary.
– Enable the external Oscillator (OSCE bit)
• PLL Bypassed External (PBE)
— The Bus Clock is based on the Oscillator Clock.
— This mode can be entered from default mode PEI by performing the following steps:
– Enable the external Oscillator (OSCE bit)
– Wait for Oscillator to start up (UPOSC=1)
– Select the Oscillator Clock as Bus Clock (PLLSEL=0).
— The PLL Clock is still on for spike filtering on Oscillator Clock.
7.1.2.2 Wait Mode
For S12CPMU Wait Mode is the same as Run Mode.
7.1.2.3 Stop Mode
This mode is entered by executing the CPU STOP instruction.
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
199