TLK3134_1 Datasheet, PDF (95/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
• Else if using clock bypass mode (JCPLL Off)
– JCPLL Mux Settings (see Figure 1-3)
– Select REFCLK input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b01 to 4/5.37120.15:14
– If Differential REFCLK used – Write 2’b00 to 4/5.37120.15:14
– Select RXBYTE_CLK (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.13:12
– If Differential REFCLK used – Write 2’b11 to 4/5.37120.13:12
– Select SERDES TX Reference Clock Input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.11:10
– If Differential REFCLK used – Write 2’b11 to 4/5.37120.11:10
– Select SERDES RX Reference Clock Input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.9:8
– If Differential REFCLK used – Write 2’b11 to 4/5.37120.9:8
– Select DELAY_CLK (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.7:6
– If Differential REFCLK used – Write 2’b11 to 4/5.37120.7:6
– Select HSTL_2X_CLK (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.5:4
– If Differential REFCLK used – Write 2’b11 to 4/5.37120.5:4
– Write 2’b00 to 16.10:9 to select SERDES TX clock as RX_CLK output (per channel)
– Write 7’h04 to 4/5.37121.6:0 to set HSTL_DIV2 to value of 4.
– Write 15’h1515 to 4/5.36864.14:0 SERDES_PLL_CONFIG to set MPY RX/TX multiplier
factor to 10
– Write 16’h5555 to 4/5.36865 SERDES_RATE_CONFIG_TX_RX to set Half Rate
• Mode Control (see Table 2-2)
– Write 1’b0 to 17.0 for RX source centered mode (per channel)
– Write 1’b0 to 17.1 for TX source centered mode (per channel)
– Write 1’b1 to 17.2 to enable 8B/10B encode decode functions (per channel)
– Write 1’b1 to 17.3 to enable 1000Base-X PCS TX & PCS RX functions (per channel)
– Write 1’b1 to 17.4 to set nibble order, LSB on rising edge, MSB on falling edge (per channel)
– Write 1’b1 to 17.5 to enable DDR data on TX/RX directions (per channel)
– Write 1’b0 to 17.6 to disable FC_PH overlay detection (per channel)
– Write 1’b1 to 17.7 to enable comma detection (per channel)
– Write 1’b0 to 17.9 to disable full DDR mode (per channel)
– Write 1’b0 to 16.8 to disable Farend Loop back (per channel)
– Write 1’b0 to 0.14 to disable loop back mode (per channel)
– Write 3’b111 to 4/5.36874.11:9 to set channel 0 TX swing setting amplitude to 1375 mVdfpp
– Write 1’b1 to 4/5.36874.8 to set channel 0 TX CM bit
– Write 3’b111 to 4/5.36876.11:9 to set channel 1 TX swing setting amplitude to 1375 mVdfpp
– Write 1’b1 to 4/5.36876.8 to set channel 1 TX CM bit
– Write 3’b111 to 4/5.36878.11:9 to set channel 2 TX swing setting amplitude to 1375 mVdfpp
– Write 1’b1 to 4/5.36878.8 to set channel 2 TX CM bit
– Write 3’b111 to 4/5.36880.11:9 to set channel 3 TX swing setting amplitude to 1375 mVdfpp
– Write 1’b1 to 4/5.36880.8 to set channel 3 TX CM bit
• RX equalization settings
– Write 4’b0001 to 4/5.36866.15:12 to turn on adaptive equalization (4’b0000 is off)
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Device Reset Requirements/Procedure
95