TLK3134_1 Datasheet, PDF (78/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
Table 2-115. SERDES_TX3_STATUS⁽¹⁾
BIT(s)
4/5.36890.0
ADDRESS: 0x901A
DEFAULT: 0x0000
NAME
DESCRIPTION
TX CH 3 TESTFAIL
When HIGH, indicates an error occurred during test pattern verification
for SERDES TX CH 3.
(1) Above status bits are only for Transmit CH 3.
BIT(s)
4/5.36891.4
4/5.36891.0
Table 2-116. SERDES_PLL_STATUS
ADDRESS: 0x901B
DEFAULT: 0x0000
NAME
DESCRIPTION
PLL_LOCK_RX
1 = Indicates PLL is locked within 10ppm of REFCLKP/N in SERDES RX
macro
PLL_LOCK_TX
1 = Indicates PLL is locked within 10ppm of REFCLKP/N in SERDES TX macro
BIT(s)
4/5.37120.15:14
4/5.37120.13:12
4/5.37120.11:10
4/5.37120.9:8
4/5.37120.7:6
4/5.37120.5:4
Table 2-117. JC_CLOCK_MUX_CONTROL
ADDRESS: 0x9100
DEFAULT: 0x3FF0
NAME
DESCRIPTION
REF_SEL[1:0]
Jitter Cleaner Reference clock select control
00 = Selects differential REFCLKP/N as jitter cleaner clock input
01 = Selects CMOS REFCLK as jitter cleaner clock input
10 = Selects recovered clock as jitter cleaner clock input
11 = Reserved
RXB_SEL[1:0]
Jitter Cleaner RXBYTECLK select control
00 = Selects RXB_DIV divider output clock as RXBYTECLK
01 = Selects recovered clock as RXBYTECLK
10 = Selects CMOS REFCLK as RXBYTECLK
11 = Selects differential REFCLKP/N as RXBYTECLK
TX_SEL[1:0]
Jitter Cleaner SERDES TX Reference clock input select control
00 = Selects jitter cleaner output clock as TX SERDES reference clock input
01 = Selects recovered clock as TX SERDES reference clock input
10 = Selects CMOS REFCLK as TX SERDES reference clock input
11 = Selects differential REFCLKP/N as TX SERDES reference clock input
RX_SEL[1:0]
Jitter Cleaner SERDES RX Reference clock input select control
00 = Selects jitter cleaner output clock as RX SERDES reference clock input
01 = Selects recovered clock as RX SERDES reference clock input (Not
Recommended)
10 = Selects CMOS REFCLK as RX SERDES reference clock input
11 = Selects differential REFCLKP/N as RX SERDES reference clock input
DEL_SEL[1:0]
Delay stopwatch clock input select control
00 = Selects delay clock divider output clock as delay stopwatch clock input
01 = Selects recovered clock as delay stopwatch clock input
10 = Selects CMOS REFCLK as delay stopwatch clock input
11 = Selects differential REFCLKP/N as delay stopwatch clock input
HSTL_SEL[1:0]
HSTL VTP 2x clock divider input select control
00 = Selects HSTL DIV clock output as HSTL VTP 2x clock divider input
01 = Selects recovered clock as HSTL VTP 2x clock divider input
10 = Selects CMOS REFCLK as HSTL VTP 2x clock divider input
11 = Selects differential REFCLKP/N as HSTL VTP 2x clock divider input
ACCESS
RO
ACCESS
RO/LL
ACCESS
RW
RW
RW
RW
RW
RW
78
Detailed Description
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