TLK3134_1 Datasheet, PDF (61/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
BIT(s)
4/5/32801.15
Table 2-64. TEST_PATTERN_STATUS
ADDRESS: 0x8021
DEFAULT: 0x0000
NAME
DESCRIPTION
Test pattern sync
status
When high, indicates that preamble for 10GFC_CJPAT/CRPAT/CJPAT
has been recovered.
BIT(s)
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Table 2-65. LANE_0_ERROR_CODE
ADDRESS: 0x8022
DEFAULT: 0xCE00
NAME
DESCRIPTION
Lane 0 error code
select.
Error code to be transmitted in case of error condition. This applies to
both TX and RX data paths. The msb is the control bit; remaining 8 bits
constitute the error code. The default value for lane 0 corresponds to
8’h9C with the control bit being 1’b1. The default values for lanes 0~3
correspond to ||LF||
BIT(s)
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Table 2-66. LANE_1_ERROR_CODE
ADDRESS: 0x8023
DEFAULT: 0x0000
NAME
DESCRIPTION
Lane 1 error code
select.
Error code to be transmitted in case of error condition. This applies to
both TX and RX data paths. The msb is the control bit; remaining 8 bits
constitute the error code. The default value for lane 1 corresponds to
8’h00 with the control bit being 1’b0. The default values for lanes 0~3
correspond to ||LF||
BIT(s)
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Table 2-67. LANE_2_ERROR_CODE
ADDRESS: 0x8024
DEFAULT: 0x0000
NAME
DESCRIPTION
Lane 2 error code
select.
Error code to be transmitted in case of error condition. This applies to
both TX and RX data paths. The msb is the control bit; remaining 8 bits
constitute the error code. The default value for lane 2 corresponds to
8’h00 with the control bit being 1’b0. The default values for lanes 0~3
correspond to ||LF||
BIT(s)
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Table 2-68. LANE_3_ERROR_CODE
ADDRESS: 0x8025
DEFAULT: 0x0080
NAME
DESCRIPTION
Lane 3 error code
select.
Error code to be transmitted in case of error condition. This applies to
both TX and RX data paths. The msb is the control bit; remaining 8 bits
constitute the error code. The default value for lane 3 corresponds to
8’h01 with the control bit being 1’b0. The default values for lanes 0~3
correspond to ||LF||
BIT(s)
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Table 2-69. RX_PHASE_SHIFT_CONTROL
ADDRESS: 0x8026
DEFAULT: 0x0000
NAME
DESCRIPTION
Lane 3 phase shift
Lane 2 phase shift
Lane 1 phase shift
When set, delays the RX data sent to the XGMII interface by one clock
cycle. (Default 1’b0)
Lane 0 phase shift
ACCESS
RO
ACCESS
RW
ACCESS
RW
ACCESS
RW
ACCESS
RW
ACCESS
RW
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