TLK3134_1 Datasheet, PDF (54/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
BIT(s)
4/5.24.12
4/5.24.11
4/5.24.10
4/5.24.3
4/5.24.2
4/5.24.1
4/5.24.0
Table 2-29. XS_LANE_STATUS
ADDRESS: 0x0018
DEFAULT: 0x0C00
NAME
DESCRIPTION
Align Status
When 1, indicates all lanes are aligned
Pattern Testing Ability Always reads 1. Able to generate test patterns
Loopback Ability
Always read 1. Has the ability to perform loopback function
Lane 3 Sync
1 = Lane 3 is synchronized
0 = Lane 3 is not synchronized
Lane 2 Sync
1 = Lane 2 is synchronized
0 = Lane 2 is not synchronized
Lane 1 Sync
1 = Lane 1 is synchronized
0 = Lane 1 is not synchronized
Lane 0 Sync
1 = Lane 0 is synchronized
0 = Lane 0 is not synchronized
BIT(s)
4/5.25.2
4/5.25.1:0
Table 2-30. XS_TEST_CONTROL
ADDRESS: 0x0019
DEFAULT: 0x0000
NAME
DESCRIPTION
Receive Test-Pattern 1 = Enables test pattern generation/verification (High/Low/Medium)
Enable
0 = Test pattern generation/verification disabled (Default)
Test-Pattern Select
00 = High frequency test pattern (Default)
01 = Low frequency test pattern
10 = Mixed frequency test pattern
11 = Reserved
BIT(s)
4/5.32768.2
4/5.32768.1
4/5.32768.0
Table 2-31. TEST_CONFIG
ADDRESS: 0x8000
DEFAULT: 0x0000
NAME
DESCRIPTION
10GFC_CJPAT Enable
When set, enables the 10G Fiber channel compliant CJPAT test pattern
generation on all 4 lanes. (Default 1’b0)
CRPAT enable
When set, enables the CRPAT test pattern generation on all 4 lanes.
(Default 1’b0)
CJPAT enable
When set, enables the CJPAT test pattern generation on all 4 lanes.
(Default 1’b0)
BIT(s)
4/5.32769.2
4/5.32769.1
4/5.32769.0
Table 2-32. TEST_VERIFICATION_CONTROL
ADDRESS: 0x8001
DEFAULT: 0x0000
NAME
DESCRIPTION
10GFC_CJPAT check
enable
When set, enables the verification of 10G Fiber channel compliant
CJPAT test mode. (Default 1’b0)
CRPAT Check Enable When set, enables the verification of CRPAT test mode. (Default 1’b0)
CJPAT Check Enable When set, enables the verification of CJPAT test mode. (Default 1’b0)
BIT(s)
4/5.32770.9
4/5.32770.8
4/5.32770.7
4/5.32770.6
Table 2-33. TX_FIFO_STATUS
ADDRESS: 0x8002
DEFAULT: 0x0000
NAME
DESCRIPTION
Lane 3 Overflow
Lane 2 Overflow
Lane 1 Overflow
When high, indicates that transmit FIFO overflow condition occurred for
the corresponding lane.
Lane 0 Overflow
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ACCESS
RO
RO
RO
RO
RO
RO
RO
ACCESS
RW
RW
ACCESS
RW
ACCESS
RW
ACCESS
RO/LH
54
Detailed Description
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