TLK3134_1 Datasheet, PDF (65/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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BIT(s)
16.15
16.11
16.10:9
16.8
16.7
16.6
16.5
16.4
16.3
16.2:0
TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
Table 2-79. PHY_CH_CONTROL_1
ADDRESS: 0x10
DEFAULT: 0x0000
NAME
DESCRIPTION
Global Write
When written as 1 the settings in 16.14:0 will affect all channels of one
device simultaneously.
When written as 0 the settings in 16.14:0 are only valid for the addressed
channel.
This value always reads zero.
Datapath Reset Control
1 = Resets channel logic excluding MDIO registers (Resets both Tx and
Rx datapaths)
Receive Parallel Output
Clock Select
00 = Selects respective channel SERDES TX clock
01 = Selects Jitter cleaned clock(Selecting the jitter cleaned clock while
the jitter cleaner PLL is disabled is not recommended)
10 = Selects respective channel SERDES RX clock
11 = Reserved
Farend Loopback
Logically OR’ed with SLOOP
When asserted high the data presented at the serial receive interface is
looped back to the serial transmit interface of the same channel via the
deserializer, the serializer and if enabled the PCS function. If 1GX PCS is
not enabled, the incoming datarate must be frequency locked (ppm 0)
with REFCLK.
Also referred to as remote loopback.
0 = Farend Loopback is disabled. (Default 1’b0)
1 = Farend loopback is enabled.
PRBS Verifier Enable
A logic 1 enables the PRBS (2^7) verifier in the receive datapath.
Logically OR'ed with the PRBSEN pin. (Default 1’b0)
PRBS Generator Enable
A logic 1 enables the PRBS (2^7) generator in the transmit datapath.
Logically OR'ed with the PRBSEN pin. (Default 1’b0)
Channel sync freeze control When set, freezes last acquired word alignment. (Default 1’b0)
Test Pattern
Generator Enable
When high activates the generator selected by bits 16.2:0. (Default 1’b0)
Test Pattern
Verifier Enable
When high activates the verifier selected by bits 16.2:0. (Default 1’b0)
Pattern Select
Test Pattern Selection
000 = High Frequency Test Pattern (Default 3’b000)
001 = Low Frequency Test Pattern
010 = Mixed Frequency Test Pattern
011 = CRPAT Long
100 = CRPAT Short
Others = Reserved
ACCESS
RW/SC
RW/SC
RW
RW
RW
RW
RW
RW
RW
RW
BIT(s)
17.15
17.14
17.13
17.12
Table 2-80. PHY_CH_CONTROL_2
ADDRESS: 0x11
NAME
Global write
Sync Status Override
TX PMA Bit Order
RX PMA Bit Order
DEFAULT: 0x3590
DESCRIPTION
When written as 1 the settings in 17.14:0 will affect all channels of one
device simultaneously. When written as 0 the settings in 17.14:0 are only
valid for the addressed channel.
This value always reads zero.
1 = Causes an override of the sync state of 1000Base-X synchronization
state machine to reflect a “1” in the sync_status (1.2) bit.
0 = Original (normal operation) sync_status value is represented in bit
1.2. (Default 1’b0)
When asserted, allows the ten bits of data given to the parallel side of
the SERDES TX macro to be flipped. This is normally set since the
SERDES transmits MSB first, and the 1000Base-X standard requires
LSB to be transmitted first. For standard based operation, the customer
may leave this bit alone. (Default 1’b1)
When asserted, allows the ten bits of data received from the parallel side
of the SERDES RX macro to be flipped. This is normally set since the
SERDES receives MSB first, and the 1000Base-X standard requires LSB
to be received first. For standard based operation, the customer may
leave this bit alone. (Default 1’b1)
ACCESS
RW/SC
RW
RW
RW
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