TLK3134_1 Datasheet, PDF (26/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
2.7.5 GMII Mode (Gigabit Media Independent Interface)
www.ti.com
DATA
CHANNEL
NUMBER
Channel 0
Channel 1
Channel 2
Channel 3
TX_EN
CONTROL
BIT
(INPUT)
TXC_[0]
TXC_[1]
TXC_[2]
TXC_[3]
Table 2-8. GMII – Lane To Functional Pin Mapping
TX_ER
CONTROL
BIT
(INPUT)
TXC_[4]
TXC_[5]
TXC_[6]
TXC_[7]
TRANSMIT
DATA BYTE
(INPUT)
TXD_[7:0]
TXD_[15:8]
TXD_[23:16]
TXD_[31:24]
RX_DV
CONTROL
BIT
(OUTPUT)
RXC_[0]
RXC_[1]
RXC_[2]
RXC_[3]
RX_ER
RECEIVE
CONTROL BIT DATA BYTE
(OUTPUT) (OUTPUT)
RXC_[4]
RXC_[5]
RXC_[6]
RXC_[7]
RXD_[7:0]
RXD_[15:8]
RXD_[23:16]
RXD_[31:24]
TRANSMIT
CLOCK
(INPUT)
TXCLK_[0]
TXCLK_[1]
TXCLK_[2]
TXCLK_[3]
RECEIVE
CLOCK
(OUTPUT)
RXCLK_[0]
RXCLK_[1]
RXCLK_[2]
RXCLK_[3]
TXCLK_[0]
SDR Rising Edge Aligned Timing
TXC_[0],TXC_[4],TXD_[7:0]
{TX_EN,TX_ER,Data0[7:0]}
{TX_EN,TX_ER,Data1[7:0]}
RXCLK_[0]
RXC_[0],RXC_[4],RXD_[7:0]
TXCLK_[0]
TXC_[0],TXC_[4],TXD_[7:0]
{RX_DV,RX_ER,Data0[7:0]}
{RX_DV,RX_ER,Data1[7:0]}
SDR Falling Edge Aligned Timing
{TX_EN,TX_ER,Data0[7:0]}
{TX_EN,TX_ER,Data1[7:0]}
RXCLK_[0]
RXC_[0],RXC_[4],RXD_[7:0]
{RX_DV,RX_ER,Data0[7:0]}
{RX_DV,RX_ER,Data1[7:0]}
Figure 2-11. GMII – Individual Channel Byte Ordering – Channel 0 Example
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Detailed Description
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