TLK3134_1 Datasheet, PDF (34/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
TXCLK
Source Centered (DDR)
TXD
TXC
t_SETUP
t_HOLD
Data
t_SETUP
t_HOLD
Data
Source Aligned (DDR)
TXD
TXC
Data
Falling Edge Aligned (Rising Edge Sampled) (SDR)
TXD
TXC
Data
Data
Data
Data
Rising Edge Aligned (Falling Edge Sampled) (SDR)
TXD
TXC
Data
Data
Figure 2-19. Transmit Interface Timing
2.7.13 Parallel Interface Data
Data placed on the XGMII transmit input bus is latched and then phase aligned to the internal version of
the transmit reference clock, 8b/10b encoded, serialized, then transmitted sequentially beginning with the
LSB of the encoded data byte over the differential high speed serial transmit pins.
The XGMII receive data bus outputs four bytes on RXD(31:0). Control character (K-characters) reporting
for each byte is done by asserting the corresponding control pin, RXC(3:0). When RXC is asserted, the 8
bits of data corresponding to the control pin is to be interpreted as a K-character. If an error is uncovered
in decoding the data, the control pin is asserted and 0xFE is output for the corresponding byte.
2.7.14 Transmission Latency
For each channel, the data transmission latency of the TLK3134 is defined as the delay from the rising or
falling edge of the selected transmit clock when valid data is on the transmit data pins to the serial
transmission of bit 0, as shown in Figure 2-20. The maximum transmit latency is a function of the mode of
operation, and is detailed in Section 4.10: Serial Transmitter/Receiver characteristics.
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Detailed Description
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