TLK3134_1 Datasheet, PDF (110/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
SIGNAL LOCATION
REFCLKP/
L1
REFCLKN
K1
VDDA_VCO
K2
VSSA_VCO
K3
VDDA_CP
L4
VSSA_CP
L5
VDD_CML
M1
VSS_CML
J1
VDD_PLL
J5
VSS_PLL
J4
VCO_TL_TST
J3
TST_OUT
J2
CP_OUT
K5
VTUNE
K4
Table 3-8. Jitter Cleaner Related Pins
VOLTAGE
VDD_CML
P
G
P
G
P
G
P
G
G
VDD_PLL
VDDA_CP
VDDA_VCO
TYPE
DESCRIPTION
Differential Reference Clock Inputs
By default, the differential reference clock (REFCLKP/N) is selected.
This default value may be changed by a mdio register (4/5.37120.15:14).
I
Must Be Externally AC Coupled
REFCLKP – DPECL REFCLK P Input
REFCLKN – DPECL REFCLK N Input Acceptable input frequency range is
50 MHz → 375 MHz. Jitter performance is optimal when using the
differential REFCLK input.
P
Jitter Cleaner – VCO Supply - 1.2 V
G
Jitter Cleaner Ground
P
Jitter Cleaner – Charge Pump - 1.2 V
G
Jitter Cleaner Ground
P
Jitter Cleaner – REFCLKP/N Input Supply - 1.2 V
G
Jitter Cleaner Ground
P
Jitter Cleaner Digital Power (1.2 V)
G
Jitter Cleaner Ground
Analog Input VCO Testability Input. This signal should be grounded in the application.
Analog
Jitter Cleaner Testability Pin. This signal should be left open
Input/Output (unconnected) in the application.
Analog Output
Charge Pump Output. If the internal Jitter Cleaner PLL is used, this signal
should be connected to the input of the external loop filter (See
Figure B-1). If the internal Jitter Cleaner PLL is not used, this node should
be left open (unconnected).
LC VCO Bias Voltage. This signal should be connected to the output of
Analog Input the external loop filter if the Jitter Cleaner PLL is used (Figure B-1). If the
internal Jitter Cleaner PLL is not used, this node should be grounded.
1
2
3
4
5
6
7
8
9
A
DGND VDDQ RXD_15 RXD_11 VDDQ RXD_9 DGND RXD_8 VDDQ
B
RXD_19 RXD_17 RXD_14 RXD_12 VDDQ RXD_10 RXC_2 RXD_7 RXD_5
C
VDDQ RXCLK_3 DGND RES1 RXD_13 RXCLK_2 VDDQ VDDQ RXD_3
D
VDDQ RXD_21 RXC_5 RXD_18 RXC_4 DGND RXCLK_1 RXD_6 RXCLK_0
E
RXD_23 RXD_24 RXD_22 VDDQ RXD_20 RXD_16 RXC_3 RXC_1 DGND
F
RXD_26 DGND VDDQ RXC_6 RXD_25 DVDD VDDQ DVDD DVDD
G
VDDQ RES2 RXD_28 RXD_27 DGND DVDD DGND DGND DGND
H
RXD_30 RXD_31 VDDQ RXC_7 RXD_29 VDDQ DGND DGND DGND
J VSS_CML TST_OUT VCO_TL_TST VSS_PLL VDD_PLL GPO4 DVDD DGND DGND
K REFCLKN VDDA_VCO VSSA_VCO VTUNE CP_OUT GPO3 DGND DGND DGND
L REFCLKP VDDO GPO1 VDDA_CP VSSA_CP GPO2 DGND DGND DGND
M VDD_CML REFCLK CODE DGND
ST TESTEN DGND DGND DGND
N
GPO0 PRTAD1 PRTAD2 PRTAD3 PRTAD4 DVDD AVDD DVDD VDDO
P
RST_N DGND VDDO AGND AGND AGND VDDT AGND VDDR
R
VDDO GPI1
TDP0
TDN0 AVDD TDP2 TDN2 AVDD RDN0
T
PRTAD0 DVDD AGND VDDT AGND AMUX0 VDDD AGND VDDT
U ENABLE PRBS_EN VDDD TDN1 TDP1 AVDD TDN3 TDP3 AVDD
Figure 3-1. Device Pinout Diagram – Part 1 (Top View)
110 Device Reset Requirements/Procedure
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