TLK3134_1 Datasheet, PDF (77/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
Table 2-110. SERDES_RX2_STATUS⁽¹⁾
BIT(s)
4/5.36885.3
4/5.36885.2
4/5.36885.1
4/5.36885.0
ADDRESS: 0x9015
DEFAULT: 0x0000
NAME
DESCRIPTION
LOSDTCT
When HIGH indicates Loss of Signal condition is detected for RX CH 2
ODDCG
LOW when SYNC is HIGH. After that toggles every cycle.
SYNC
When comma detection is enabled, this bit is HIGH when an aligned
comma is received.
RX CH 2 TESTFAIL
When HIGH, indicates an error occurred during test pattern verification
for SERDES RX CH 2.
When ST = 0, this bit status is valid when PRBS_EN pin is set or when
SERDES RX test pattern registers bits are set
When ST = 1, this bit status is valid only when SERDES RX test pattern
verification bits are set
(1) Above status bits are only for Receive CH 2.
Table 2-111. SERDES_RX3_STATUS⁽¹⁾
BIT(s)
4/5.36886.3
4/5.36886.2
4/5.36886.1
4/5.36886.0
ADDRESS: 0x9016
DEFAULT: 0x0000
NAME
DESCRIPTION
LOSDTCT
When HIGH indicates Loss of Signal condition is detected for RX CH 3
ODDCG
LOW when SYNC is HIGH. After that toggles every cycle.
SYNC
When comma detection is enabled, this bit is HIGH when an aligned
comma is received.
RX CH 3 TESTFAIL
When HIGH, indicates an error occurred during test pattern verification
for SERDES RX CH 3
When ST = 0, this bit status is valid when PRBS_EN pin is set or when
SERDES RX test pattern registers bits are set
When ST = 1, this bit status is valid only when SERDES RX test pattern
verification bits are set
(1) Above status bits are only for Receive CH 3.
Table 2-112. SERDES_TX0_STATUS⁽¹⁾
BIT(s)
4/5.36887.0
ADDRESS: 0x9017
DEFAULT: 0x0000
NAME
DESCRIPTION
TX CH 0 TESTFAIL
When HIGH, indicates an error occurred during test pattern verification
for SERDES TX CH 0.
(1) Above status bits are only for Transmit CH 0.
Table 2-113. SERDES_TX1_STATUS⁽¹⁾
BIT(s)
4/5.36888.0
ADDRESS: 0x9018
DEFAULT: 0x0000
NAME
DESCRIPTION
TX CH 1 TESTFAIL
When HIGH, indicates an error occurred during test pattern verification
for SERDES TX CH 1.
(1) Above status bits are only for Transmit CH 1.
Table 2-114. SERDES_TX2_STATUS⁽¹⁾
BIT(s)
4/5.36889.0
ADDRESS: 0x9019
DEFAULT: 0x0000
NAME
DESCRIPTION
TX CH 2 TESTFAIL
When HIGH, indicates an error occurred during test pattern verification
for SERDES TX CH 2.
(1) Above status bits are only for Transmit CH 2.
ACCESS
RO
RO
RO
RO
ACCESS
RO
RO
RO
RO
ACCESS
RO
ACCESS
RO
ACCESS
RO
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