TLK3134_1 Datasheet, PDF (32/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
2.7.11 NBID Mode (Nine Bit Interface DDR)
DATA CHANNEL
NUMBER
Channel 0
Channel 1
Channel 2
Channel 3
Table 2-14. NBID – Lane To Functional Pin Mapping
TRANSMIT DATA 9 BITS
(INPUT)
{TXC_[0],TXD_[7:0]}
{TXC_[1],TXD_[15:8]}
{TXC_[2],TXD_[23:16]}
{TXC_[3],TXD_[31:24]}
RECEIVE DATA 9 BITS
(OUTPUT)
{RXC_[0],RXD_[7:0]}
{RXC_[1],RXD_[15:8]}
{RXC_[2],RXD_[23:16]}
{RXC_[3],RXD_[31:24]}
TRANSMIT CLOCK
(INPUT)
TXCLK_[0]
TXCLK_[1]
TXCLK_[2]
TXCLK_[3]
TXCLK_[0]
DDR Source Centered Timing
TXC_[0], TXD_[7:0]
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
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RECEIVE CLOCK
(OUTPUT)
RXCLK_ [0]
RXCLK_ [1]
RXCLK_ [2]
RXCLK_ [3]
RXCLK_[0]
RXC_[0], RXD_[7:0]
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
TXCLK_[0]
TXC_[0], TXD_[7:0]
DDR Source Aligned Timing
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
RXCLK_[0]
RXC_[0], RXD_[7:0]
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
Figure 2-17. NBID – Individual Channel Byte Ordering – Channel 0 Example
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Detailed Description
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