TLK3134_1 Datasheet, PDF (79/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
BIT(s)
4/5.37121.14:8
4/5.37121.6:0
Table 2-118. JC_VTP_CLK_DIV_CONTROL
ADDRESS: 0x9101
DEFAULT: 0x0E06
NAME
DESCRIPTION
HSTL_DIV[6:0]
HSTL Output Divider 1 Value. See Figure 1-3. This value is the divider value for
the clock which runs the HSTL impedance compensation controller. The target
output frequency for the impedance controller clock is 40 Mhz. If the jitter
cleaner is not enabled, this value is not used.
Legal programmed values are greater than or equal to 6
HSTL_DIV2[6:0]
HSTL Output Divider 2 Value. See Figure 1-3. This value is the divider value for
the HSTL impedance compensation controller. The target output frequency for
this clock is 40 MHz. When the jitter cleaner (HSTL_DIV1) is used, this value
should be provisioned to 6 decimal. When the jitter cleaner (HSTL_DIV1) is not
used, this divider value should be provisioned according to the following
equation:
Value = (Parallel Output Byte Clock Frequency / 40 Mhz)
Legal programmed values are 1, and greater than or equal to 4
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BIT(s)
4/5.37122.14:8
4/5.37122.2:1
4/5.37122.0
Table 2-119. JC_DELAY_STOPWATCH_CLK_DIV_CONTROL
ADDRESS: 0x9102
NAME
DEL_DIV[6:0]
Delay stop watch lane
select[1:0]
Delay stop watch clock
enable
DEFAULT: 0x0600
DESCRIPTION
Delay Measurement Clock Output Divider Value. See Figure 1-3.
Controls the clock divider for the delay stop watch function. This
value should be provisioned to decimal 6.This value is only used
when the delay calculator circuit is enabled.
Legal programmed values are greater than or equal to 6
Lane select to enable comma monitor. Valid only when 37122:0 is
“1”
00 = Comma monitor enabled on Lane 0
01 = Comma monitor enabled on Lane 1
10 = Comma monitor enabled on Lane 2
11 = Comma monitor enabled on Lane 3
When set, enables Delay stop watch clock
ACCESS
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Table 2-120. JC_DELAY_STOPWATCH_COUNTER
BIT(s)
ADDRESS: 0x9103
NAME
4/5.37123.15:0
Delay stop watch
counter[15:0]
DEFAULT: 0x0000
DESCRIPTION
Delay Counter. This value represents the latency in number of clock
cycles. This counter resets on read and will return 16’h0000 if its read
before rx comma is received. If latency is more than 16’hFFFF clock
cycles then this counter returns 16’hFFFF.
ACCESS
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Table 2-121. JC_REFCLK_FB_DIV_CONTROL
BIT(s)
ADDRESS: 0x9104
NAME
4/5.37124.15 REFDIV_EN
4/5.37124.14:8 REF_DIV[0:6]
4/5.37124.7 FBDIV_EN
4/5.37124.6:0 FB_DIV[6:0]
DEFAULT: 0x018E
DESCRIPTION
1 = Enables Reference clock divider
0 = Disables Reference clock divider
Controls the clock divider value for the reference clock. See Figure 1-3,
and Appendix A for provisioning details
Note: REF_DIV[6:0] = 4/5.37124.8:14.
(Example: To program REF_DIV to decimal value 4, 14:8 needs to be set
to 7’b0010000)
1 = Enables Feedback divider
0 = Disables feedback divider
Controls the feedback divider value
See Figure 1-3, and Appendix A for provisioning details.
Note: JC_CHARGE_PUMP_ CONTROL (4/5.37126) needs to be set
accordingly based on FB_DIV range. Refer Table 2-124: Charge Pump
Control Setting (CP_CTRL)
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